1. Field of the Invention
The present invention relates to the generation of timing signals (or internal clock signals) used in semiconductor integrated circuits (ICs), and more particularly to a timing signal generation circuit and a data transfer circuit, etc., utilizing the timing signal generation circuit.
2. Description of the Related Art
In recent years, semiconductor ICs such as microprocessors and high-speed memories are expected to operate at inconceivably high speeds, e.g., 80 MHz or 100 MHz, and even 150 MHz or 200 MHz. However, circuit chips required to operate at such high speeds are susceptible to the problem of phase shifting of clock signals, which hinders their high-speed operation capabilities.
This problem will be described with reference to FIGS. 33 and 47 below.
FIG. 46 is a schematic diagram showing a manner in which clock signals are input to conventional semiconductor ICs (semiconductor chips). A clock signal generation circuit receives an external clock signal from a timing signal generation circuit located on the same circuit board, via an external clock signal input terminal. The clock signal generation circuit generates an internal clock signal which is in synchronization with the external clock signal. The generated internal clock signal is supplied to various circuits in the semiconductor chip. The external clock signal output from the timing signal generation circuit on the circuit board is also supplied to the external clock signal input terminals of other semiconductor chips on the same circuit board. Various processes are performed by the semiconductor chips using the internal clock signal (generated by the clock signal generation circuit) as a timing signal. For example, data may be input from an output circuit to the signal input terminals of other semiconductor chips via a data output terminal, in accordance with a timing signal.
FIG. 47A shows the waveform of an external clock signal generated by the above-mentioned timing generation circuit on the circuit board. FIGS. 47B and 47D show a signal waveform taken at a clock terminal of an output circuit. Specifically, FIG. 47B describes the case with only a small internal delay. FIG. 47D describes the case with a large internal delay. FIG. 47C shows an output waveform from a semiconductor chip having a small internal delay. FIG. 47D shows an output waveform from a semiconductor chip having a large internal delay. In FIG. 47C, the output from the semiconductor chip becomes stable by the time a subsequent semiconductor chip makes an access for reading out a signal. On the contrary, in FIG. 47E, the output from the semiconductor chip is not stable or established yet by that time.
As shown in FIG. 46 and FIGS. 47A to 47E, the data in an output signal from an output circuit of one semiconductor chip can be stably read by a subsequent semiconductor chip in synchronization with a clock signal on the circuit board as long as the cycle of the clock signal is sufficiently longer than the internal delay time of the clock taken at the output circuit of the former semiconductor chip. On the other hand, when the cycle of a clock signal is not sufficiently longer than the internal delay time of the clock (taken at the output circuit of the former semiconductor chip), the data in the output signal from that output circuit is not stabilized yet when it is read by a subsequent semiconductor chip.
In order to solve the above-mentioned problem of internal delay, a circuitry technique called PLL (PhaseLocked Loop) is conventionally employed in many cases. This technique will be described below. (See literature such as IEEE Journal of Solid state Circuits vol. 27, no 11, November 1992, p. 1599 for conventional PLL techniques.)
The main cause for the internal delay time of a clock signal, taken at an output circuit of a semiconductor chip, is the delay time of a clock driver. The delay time of a clock driver is typically increased by a large capacitance resulting from a large number of destinations of clock driver lines, which increases the time required for charging/discharging of the clock driver. FIG. 48 shows the schematic configuration of a PLL circuit for eliminating the delay time of a clock driver. Conventional PLL circuits adopt the configuration shown in FIG. 48 in order to minimize such delay in a clock driver.
First, as shown in FIG. 48, an external clock signal is input to one end of a phase difference detection circuit. Another end of the phase difference detection circuit is coupled to the output of a clock driver (i.e., a clock driver line). A voltage controlled oscillator (VCO) is controlled by the output of the phase difference detection circuit. The output of the VCO controls the clock driver. Specifically, the phase difference detection circuit controls the voltage at a control terminal of the VCO so that the entire circuit becomes stable when the output of the clock driver matches the external clock signal in terms of both phases and cycles. In that state, the apparent delay time caused by the clock driver becomes zero. Thus, conventional PLL circuits can provide a large advantage of eliminating the apparent delay time caused by the clock driver.
However, the above-described conventional technique has a problem of a long "setup time", which is defined as the time required from the beginning of the generation of a given clock signal till it becomes possible to stably generate the clock signal. The setup time can take several dozen clocks to several thousand clocks (amounting to several microseconds to several milliseconds in some extreme cases). Until the setup time elapses, normal operation cannot be expected.